1. Field of the Invention
The present invention relates to an art of driving a display panel composed of a set of cells that are display elements having a memory function. More particularly, this invention is concerned with a driving method employed in writing display data in an alternating current (AC) type plasma display panel (PDP), and a panel in which the driving method is implemented.
A known display apparatus having a plasma display panel has three major problems as described below.
The first problem is a problem of invalid glowing occurring at a reset step. Full-screen writing discharge and full-screen self-erasure discharge have been used as a means for reset in the past. This known approach is adopted as a technique for neutralizing wall charge uniformly and stabilizing succeeding addressing discharge. Even in a full-screen erased state in which no display data is written, glowing takes place at a certain intensity. This leads to deteriorations of display contrast and display quality. Taking a known panel for instance, an amount of glow occurring at a reset step within each subfield reaches approximately 4 cd/M.sup.2. A maximum gray-scale level attainable when cells are lit is approximately 200 cd/m.sup.2. Thus, even in a dark room, the contrast is only 50:1.
The second problem lies in a voltage to be applied at an addressing step. For inducing addressing discharge, voltages that are higher than a discharge start voltage are applied to second electrodes and third electrodes respectively. It is therefore hard to minimize the power consumptions and breakdown voltages of a scan driver and address driver for driving electrodes independently. This leads to an increase in the cost of a display apparatus.
The third problem lies in the speed of addressing discharge. In a subfield method enabling gray-scale display, it is necessary to define many subfields within a predetermined time of one frame. It is essential to shorten an addressing period within each subfield which does not contribute to glowing. According to the known approach, discharge is induced in both X electrodes and Y electrodes using discharge occurring in addressing electrodes and Y electrodes as a trigger, thus forming wall charge needed for sustaining discharge. The time of 3 microseconds is therefore required for one addressing cycle. The number of lines that can be driven for a certain period of time and the number of subfields that can be defined therefor are therefore limited.